Power-gating (e.g., Sleep-mode) is a popular technique to reduce power consumption of circuit blocks. During power-gating inactive circuit blocks are disconnected from the power supply to minimize leakage currents. One such conventional power gating scheme 100 is disclosed by FIG. 1A. Scheme 100 illustrates an external power source e.g., a Battery 101, which provides input supply to a voltage regulator (VR) 102. VR 102 then generates a regulated supply (having current Iext) to a power supply node VCC,global of an integrated circuit (e.g., Chip 103). Here, Chip 103 includes a processing core (i.e., Core 104) which operates on a power on supply VCC,core provided by a p-type sleep transistor MPs. Core 104 is represented as a load having load capacitance CL and circuits that have leakage current Ileak. The sleep transistor MPs is controllable by a Sleep signal. When the sleep transistor MPs is turned ON, VCC,global is shorted with VCC,core, and Core is provided with power to operate. When the sleep transistor MPs is turned OFF, VCC,global is disconnected from VCC,core, and Core 104 is powered down i.e., power gated.
In conventional power-gating schemes, electrical charge residing on the capacitive power distribution network is lost through leakage currents of the power-gated circuit block. FIG. 1B illustrates a plot 120 of three waveforms associated with scheme 100 of FIG. 1A. Here, x-axis is time, and y-axis for the top two waveforms is voltage (ranging from Vcc to Vss) and the bottom waveform is current (ranging from OA to Iactive). The first signal from the top is Sleep signal. When Sleep is logical low, sleep transistor MPs is turned ON. When sleep transistor MPs is turned ON, VCC,core is the same as VCC,global (i.e., VCC), and Iext is equal to Iactive (i.e., current consumed by active Core 104). When Sleep asserts i.e., Sleep signal transitions from logical low to logical high, sleep transistor MPs is turned OFF. Here, VCC,core is disconnected from VCC,global. VCC,core then begins to decay (i.e., CL losses charge) through leakage current Ileak,ss, and reaches a steady state level of Vxss. This charge loss is a limitation of existing power gating schemes. When Sleep de-asserts, sleep transistor MPs is turned ON, and VCC,core rises to VCC,global (i.e., VCC) level, and Iext becomes equal to Iactive (i.e., current consumed by active Core 104).
However, a shortcoming of conventional power-gating scheme 100 is that charges on the gated power grid (i.e., VCC,core) leak away due to leakage currents in Core 104 after entering sleep state, and VCC,core is eventually discharged to a voltage level close to ground (i.e., final voltage level which is given by the voltage divider consisting of the high-impedance MPs header devices and the equivalent impedance of the core). Upon wake-up, (i.e., when MPs is turned ON) prior to resuming computation by Core 104, VCC,core is ramped up again, typically with a current Iext provided by external VR 102. The energy loss due to the unintended VCC,core line discharge and subsequent charging process preponderates in case of short sleep periods. The charge loss observed when Sleep is enabled (i.e., Sleep is logically high) limits the energy savings arising from power-gating, which leads to a minimum sleep time requirement for net energy savings, and consequently limits the frequentness of beneficially entering the sleep state.